Altera Corporation has released Update 2 for Quartus II version 15.0 is a multiplatform design environment that easily adapts to your specific needs in all phases of FPGA and CPLD design. The Quartus II software delivers the highest productivity and performance for Altera FPGAs, CPLDs, and SoCs.
- Time-Proven Productivity Leadership for FPGA Design Software
Time-proven productivity leadership is a key factor in deciding which FPGA platform to adopt. If you are looking for a proven, easy-to-use software platform for your next programmable logic design, look no further. Altera's Quartus II software provides everything you need to design with Altera PLDs, including FPGAs, SoCs, and CPLDs. It is a complete development package that comes with a user-friendly GUI and best-in-class technology to help you bring your ideas into reality.
- Time-Proven Productivity Tools
Altera has a proven track record for productivity leadership. Over the years, Altera delivered a host of tools and features to enhance productivity, many of which are the first in the industry.
Recently, Altera became the first in the industry to announce the Altera SDK for OpenCL. Combining Open Computing Language (OpenCL), an open standard parallel programming language, with the parallel performance capabilities of an FPGA provides a powerful solution for system acceleration. The Altera SDK for OpenCL is in full production release.
OpenCL and the OpenCL logo are trademarks of Apple Inc. used by permission by Khronos.
- Continuous Compilation Time Reduction
With faster compile times, you can improve your productivity by completing multiple design iterations per day. Faster compile times allow you to effectively develop complex designs that leverage the great capabilities of today's FPGAs.
The Quartus II software has seen almost a decade of compile time improvements, with an average annual compile time improvement of 20 percent. Altera's advanced place-and-route algorithms contribute to compilation time reduction by allowing you to quickly find the best results based on four cost criteria - timing, congestion, wire length, and power minimization.
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