Cadence SPB OrCAD 16.60.062 Hotfix | 1.7 Gb
Cadence Design Systems Ltd., a world-renowned provider of EDA software, has released update (HF62) for Cadence SPB OrCAD 16.60, software a comprehensive package design of electronic circuits, analog and digital simulation, IC design of programmable logic and custom circuits, as well as the development and preparation for the production of printed circuit boards.
Cadence Design Systems, Inc., a leader in global electronic design innovation, launched the Cadence OrCAD 16.6 design solution with new features, enhanced customization capabilities, and 20 percent simulation performance improvements that provide customers a shorter, more predictable path to product creation.
This latest release offers numerous improvements to tool usability and performance, but at the heart of 16.6 are three key benefits: enhanced miniaturization capabilities, timing-aware physical implementation and verification for faster timing closure, and the industry's first electrical CAD team collaboration environment for PCB design using Microsoft SharePoint technology.
CCRID PRODUCT PRODUCTLEVEL2 TITLE
1012606 ALLEGRO_EDITOR REPORTS Natural sort option for Report output
1408218 ALLEGRO_EDITOR MANUFACT Specifying the Offset value results in unexpected value of the NC Route coordinates in the .rou file
1440509 ALLEGRO_EDITOR DescriptionTING Ratsnest do not follow the refdes position when Descriptionting the BOTTOM layer with the 'Mirror' option
1444144 ALLEGRO_EDITOR DRC_CONSTR The 'add taper' command generates line to line spacing DRC
1471275 SCM UI Allegro System Architect (SCM) - Allow sorting on the pin number field in the Matrix view
1474764 ALLEGRO_EDITOR PLACEMENT In SPB166 Hotfix 56, the place replicate create command does not produce desired results if the fanout is marked
1474894 ALLEGRO_EDITOR PLACEMENT Place replicate fails to include vias when the module is applied to other circuits.
1485931 ALLEGRO_EDITOR INTERFACES Errors generated when importing IDF in an existing board file
1487603 SIP_LAYOUT WIREBOND SiP Layout XL - Add multibondwire option to non-standard wirebonding
1490311 SCM OTHER Block Packaging reports duplication when it should not
1491272 ALLEGRO_EDITOR EXTRACT Incorrect information exported to DXF if the value of SeparateSlotHoleLegend is set to 'yes'
1491521 F2B PACKAGERXL Packager reports error (SPCODD-269) when there are duplicate subdesign suffixes - need a clearer message
1492013 CONCEPT_HDL CORE Stale PNN properties not cleared from schematic on packaging design (backannotation)
1492703 CONCEPT_HDL OTHER 'Global Property Display' not working for symbol edit
1495296 SIG_EXPLORER OTHER The T-point sequence in SigXplorer is different from the layout
1495789 ALLEGRO_MFG_OP CORE DFM checker checks for laser vias ( LVDC, LVDP, LVDT )
1496286 ALLEGRO_EDITOR DescriptionTING Export PDF is not exporting hidden, phantom, and dotted line types
1499051 ALLEGRO_EDITOR DescriptionTING PDF Publisher reports error for a donut shape model in the layout - 'Shape symbol cannot have a void in a shape'
1499380 SIP_LAYOUT DEGASSING Oblong shape degassing voids are not created correctly
1499538 ALLEGRO_EDITOR PAD_EDITOR Pad_designer does not allow layer name change from Begin_layer to diepad1_top; dbdoctor does not fix this
1500422 ALLEGRO_EDITOR SKILL SKILL function, axlTriggerSet, results in PCB Editor crashing at launch
1500659 FLOWS PROJMGR Need the ability to ensure that the standard library is not added to the project libraries list by default
1500725 F2B PACKAGERXL Unable to clear pstprop.dat file conflicts
1501139 ALLEGRO_EDITOR PADS_IN Pads_in creates pastemask for Through Hole padstacks
1501165 F2B DESIGNVARI TDO does not manage overlay files and variant_roz1040660_1.ba cannot be created unless variant_merged.dat is checked out
1501774 ALLEGRO_EDITOR OTHER PDF Publisher: If text is attached to an object, the object is also printed in the PDF
1501898 F2B DESIGNVARI Variant custom variables are visible in the schematic border but are not there in the Variant Details form
1501974 F2B PACKAGERXL 'Feedback has found Illegal pin swap(s)' error although the pin was already swapped and fed back (B2F) to DE-HDL
1502782 ALLEGRO_EDITOR SCHEM_FTB Allegro System Architect (SCM) - Export Physical stops unexpectedly without any errors or warnings
1503551 APD STREAM_IF In SPB166 Hotfix 60, error reported if a self-intersecting polygon outline exists at a specific location
1504093 ASI_SI GUI View Topology and Waveform buttons overlap when Signal Analysis window is resized
1504767 CONSTRAINT_MGR SCHEM_FTB Constraint Manager generates errors if the 'sNoF2BFlow' property is added to the Constraint Manager Dictionary
1505497 SIP_LAYOUT LOGIC Assign net fails to fully connect propagated items
1506110 ALLEGRO_EDITOR DRC_CONSTR No DRC shown when a text on etch layer is overlapped on mechanical pin
1506654 CONCEPT_HDL INTERFACE_DESIGN Netgroups broken when moving
1506983 ALLEGRO_EDITOR SKILL axlBackDrill SKILL command crashes PCB Editor after backdrill analysis is run when App mode is set to None
About Cadence Design Systems, Inc.
Cadence enables global electronic design innovation and plays an essential role in the creation of today's integrated circuits and electronics. Customers use Cadence software, hardware, IP, and services to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems. The company is headquartered in San Jose, Calif., with sales offices, design centers, and research facilities around the world to serve the global electronics industry.
Name: Cadence SPB OrCAD
Version: (32bit) 16.60.062 Hotfix
OS: Windows XP / Vista / Seven
System Requirements: Cadence SPB OrCAD 16.60.000 - 16.60.061
Size: 1.6 Gb