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16-06-2021, 14:19

Simple FIFO Design and Simulation using Verilog HDL

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Simple FIFO Design and Simulation using Verilog HDL
Simple FIFO Design and Simulation using Verilog HDL
MP4 | Video: h264, 1280x720 | Audio: AAC, 44.1 KHz, 2 Ch
Genre: eLearning | Language: English + srt | Duration: 9 lectures (1h 6m) | Size: 328.1 MB

Practical learning of FIFO design using Verilog
What you'll learn:
Basics of FIFO
Design implementation and verification the FIFO using Verilog HDL
Architecture of FIFO

Requirements
Basics of Digital Logic Design
Verilog HDL

Description
Main purpose of this course is, FIFO can be extensively used in many different projects. As a FIFO is fundamental design and which is used as module in many different projects. Which is used to transfer the bytes of data from one module to another even when these two modules working with two different speed of operation.

This is course is essential for Undergraduate students for knowing fundamentals and implementation of FIFO.

This is a Practical course for Simple FIFO design and it gives clear understanding of Architecture FIFO and modules inside the FIFO, input and output signals and How write and read process can be done in FIFO. Fundamental understanding how the read write operations compare with Memory (RAM). How address generated internally using counters ( like write counter or pointer, read counter or pointer), How to know status of FIFO like full or empty.

This course shows complete implementation FIFO using Verilog HDL. Here written the Verilog HDL code for FIFO design and developed the Test bench environment with extensively used Tasks in verilog HDL. Also shows how run the simulation on edaplayground and how to detect and analyze the errors and how to analyze the results in the console output and waveform output.

Who this course is for
Electronics engineering students
Project Students in Verilog HDL
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